Announcing the Intel S/W Products Workshop

November 29th - November 30th 2010, CERN

Inside CERN openlab III collaboration, Intel is proposing a two-day workshop for CERN’s community specifically dedicated to new Intel s/w products that will be soon available to the market (launch planned in November) . This session will provide CERN’s software developers with deep insight into new features and tools helping the community to leverage on today’s and future CPU micro-architectures.

Hans Pabst and Levent Akyil (Intel SSG), will lead these two days addressing Array Building Block ArBB (aka Ct), and VTune™ Amplifier XE 2011. We are also planning hands-on exercises using real code samples from the LHC applications. The workshop will take place on 29th-30th November 2010, in the Kjell Johnsen Auditorium (building 30-7-018).

The preliminary agenda is the following:

►    November 29th: Array Building Block (ArBB) Training and Hands-on Labs

• Part I - Introduction to Intel Array Building Blocks (3 hours)

  • Intel ArBB Overview, and Q&A

  • LAB 1: Setup, Doku, Debugging, “Two Scalars”, “Scoped Timer”

  • Functions and Kernels, Containers and Parallelism

  • LAB 2: “Function vs. Map”, “Binding”, “Range Interface”

• Part II - Advanced Performance Analysis

  • User-defined Types and Memory Model

  • LAB 1: “Complex”, “Intervals”

  • Performance Optimization Hints

  • LAB 2: “Matrix-Vector”, “Capture/Closure”, “Loop Unrolling”

  • Software Design Aspects

  • LAB 3: “Heat Dissipation” (incl. Demo)

  • Placeholder Topic: Perf. Analysis, KNF, or ArBB Schedule

  • Summary

  • Q&A

►    November 30th: VTune Amplifier XE Training and Hands-on Labs

• Part I - Introduction to VTune Amplifier XE (3 hours)

  • Intel® VTune™ Amplifier XE Overview

  • High Level Features

  • Analysis types

  • Thread Profiling

  • Labs

  • Summary

• Part II - Advanced Performance Analysis (4 hours)

  • Intel® VTune™ Amplifier XE and Event Based Sampling Technology Overview

  • High Level Intel® VTune™ Amplifier XE Features

  • Introduction to Performance Monitoring Unit (PMU)

  • Event Based Performance Analysis Overview

  • Performance Analysis Methodology

  • Labs (for code efficiency, memory analysis, flops)

  • Summary

  • Q&A

The workshop is open to interested people in IT (as well as to physicists). Please confirm your presence and /or extend this invitation to colleagues who will be willing to participate. Everybody should plan to bring a laptop for accessing the openlab servers during the exercises.

If you want to attend this workshop please mail your reply to Sverre Jarp: Sverre(dot)Jarp(at)cern(dot)ch.
http://software.intel.com